Typically, when a power supply is initially turned on to supply power to a circuit, the voltage level of the power from the power supply is unstable. For example, if the power supply is designed to supply a 5 V signal, the actual voltage may be too low and may fluctuate too much to correctly drive the circuit when the power supply is initially activated. Also, in order to provide a stable voltage during the initial period after the power supply is turned on, a stable 12 V signal may be applied to the circuit from an external source until the 5 V signal has stabilized. When a power signal of the power supply (and/or the external source) is applied to drive an oscillator circuit used to generate a clock signal for a semiconductor device, the gain of the oscillator circuit is dependent upon the voltage of power signal. Therefore, oscillator circuits incorporate amplifying circuits which vary the gain of the circuit so that the gain of the circuits change based on the voltage of the power signal. As a result, an adequate clock signal can be output from the oscillator circuits as soon as possible.
FIG. 12 is a circuit diagram of a conventional oscillator circuit utilized in semiconductor devices. As shown in the figure, the oscillator circuit comprises a feedback resistor 1, a quartz oscillator 3, capacitors 4 and 5, an amplifying unit containing first and second amplifying circuits 21 and 22, a Schmitt trigger circuit 23, and an inverter 24.
The first amplifying circuit 21 comprises first and second P-channel MOS field-effect transistors ("P-type transistors") P1 and P2 and first and second N-channel MOS field-effect transistors ("N-type transistors") N1 and N2. The transistors P1, P2, N1, and N2 are sequentially connected in series between the supply voltage V.sub.CC and ground. The second amplifying circuit 22 comprises a third P-type transistor P3 and a third N-type transistor N3 which are also connected in series between the supply voltage V.sub.CC and ground.
The feedback resistor 1 and the quartz oscillator 3 are connected between the gates of the transistors P2 and N1 (i.e. the input terminal) and the drains of the transistors P2 and N1 (i.e the output terminal) of the first amplifying circuit 21. Also, the resistor 1 and oscillator 3 are connected to the gates of the transistors P3 and N3 (i.e. the input terminal) and the drains of transistors P3 and N3 (i.e. the output terminal) of the second amplifying circuit 22.
The inverter 24 inputs a gain control signal GAIN1 and inverts such signal GAIN1 to produce an inverted gain control signal GAIN1*. The gain control signal GAIN1 is supplied to the gate of the first P-type transistor P1, and the inverted gain control signal GAIN1* is supplied to the gate of the second N-type transistor N2. Also, the Schmitt trigger circuit 23 is connected to the drains of the transistors P2 and N1 of the first amplifyirg circuit 21 and the drains of the transistors P3 and N3 of the second amplifying circuit 22.
As shown by the above configuration, the oscillator 3 generates an oscillation signal X1, and the signal X1 is supplied to the gates of the transistors P2 and N1 of the first amplifying circuit 21 and to the gates of the transistors P3 and N3 of the second amplifying circuit 22. The first amplifying circuit 21 amplifies the signal X1 based on the gate control signal GAIN1. Specifically, when the signal GAIN1 equals "L", the inverter 24 inverts such signal GAIN1 to produce an inverted gain control signal GAIN1* which equals "H". Accordingly, the gain control signal GAIN1 turns ON the first P-type transistor P1, the inverted gain control signal GAIN1* turns ON the N-type transistor N2, and the first amplifying circuit 21 is enabled.
Since the transistors P3 and N3 of the second amplifying circuit are directly connected between the supply voltage V.sub.CC and ground, they are always enabled. Therefore, the oscillation signal X1 is amplified based on the gain of both the first and second amplifying circuits 21 and 22 to produce the output signal X2.
On the other hand, when the gain control signal GAIN1 equals "H", the inverted gain control signal GAIN1* equals "L". Thus, the P-type transistor P1 and the N-type transistor N2 are both turned OFF, and the oscillation signal X1 is amplified based on only the gain of the second amplifying circuit 22 to produce the output signal X2.
The output signal X2 is fed back via the feedback resistor 1 and input again to the amplifying circuits 21 and 22. As a result the signal X2 is amplified again to produce a new amplified signal X2. The output signal X2 is also output to the Schmitt trigger circuit 23, and the circuit 23 shapes the waveform of the output signal X2 to produce a clock signal X0. The clock signal X0 is then supplied to a microcomputer (not shown) to synchronize the operations of the microcomputer.
When the power supply V.sub.CC for the oscillator circuit is initially turned ON, the gain signal GAIN1 equals "L". Therefore, the first amplifying circuit 21 is enabled, and both circuits 21 and 22 amplify the oscillation signal X1 to produce the output signal X2. Also, the output signal X2 is fed back to the amplifying circuits 21 and 22 to be amplified again so that the oscillation continues. The Schmitt trigger circuit 23 inputs the signal X2 and outputs the corresponding clock signal X0. After the oscillating operation of the oscillator circuit becomes stable, the gain control signal GAIN1 is set to equal "H", and the first amplifying circuit 21 is disabled. As a result, the gain of the amplifying unit of the oscillator circuit is reduced. In other words, only the second amplifying circuit 22 continues to amplify the signal X1 to continue the oscillation operation in conjunction with the quartz oscillator 3. As shown above, the gain of the amplifying unit of the oscillation circuit can be changed in accordance with the value of the control signal GAIN1.
FIG. 13 is a circuit diagram of another conventional oscillating circuit which is disclosed in Japanese Laid-Open Patent Application No. 3-76404. The oscillating circuit is initially supplied with a 12 V signal from an external source until a 5 V signal from a power supply stabilizes. Afterwards, the circuit is supplied with the 5 V signal. Therefore, the amplifying Circuits are initially controlled to have a high gain which incrementally decreases as the 5 V signal becomes more stable.
As shown in the figure, the oscillation circuit comprises a feedback resistor 1, a quartz oscillator 3, capacitors 4 and 5, a power supply voltage detecting circuit 12, a multiplexer 13, a time detecting circuit 14, an amplifying unit 15, and an inverter 24.
The amplifying unit 15 contains first to fourth amplifying circuits. The first amplifying circuit includes P-type transistors 8a and 9a and N-type transistors 10a and 11a, and the transistors 8a, 9a, 10a, and 11a are sequentially connected in series between the supply voltage V.sub.CC and ground. The second amplifying circuit includes P-type transistors 8b and 9b and N-type transistors 10b and 11b, and the transistors 8b, 9b, 10b, and 11b are sequentially connected in series between the supply voltage V.sub.CC and ground. The third amplifying circuit includes P-type transistors 8c and 9c and N-type transistors 10c and 11c, and the transistors 8c, 9c, 10c, and 11c are sequentially connected in series between the supply voltage V.sub.CC and ground. Finally, the fourth amplifying circuit contains P-type transistors 8d and 9d and N-type transistors 10d and 11d, and transistors 8d, 9d, 10d, and 11d are sequentially connected in series between the supply voltage V.sub.CC and ground.
The power supply voltage detecting circuit 12 detects the level of the power supply voltage V.sub.CC output from the power supply and generates four detection signals Q1 to Q4 based on such level. When the power supply is initially turned ON and the oscillator circuit begins generating the output signal X2, the voltage V.sub.CC of the power supply is initially high and gradually decreases to a constant voltage V.sub.CC. As a result, the power supply voltage detecting circuit 12 initially outputs the detection signal Q1, sequentially outputs the signals Q1 and Q2 and the signals Q1, Q2, and Q3 as the voltage V.sub.CC decreases, and finally outputs the signals Q1, Q2, Q3, and Q4 when the voltage V.sub.CC becomes constant.
The time detecting circuit 14 detects the amount of time that has elapsed since power was first supplied to the oscillation circuit and outputs detection signals Y1 to Y4 based on the elapsed time. In particular, when the power is first supplied, the timing detecting circuit 14 outputs the signal Y1. Then, as time elapses, the detecting circuit 14 outputs the signals Y1 and Y2 followed by the signals Y1, Y2, and Y3. Finally, after a certain period of time has elapsed, the time detecting circuit 14 outputs the signals Y1, Y2, Y3, and Y4.
The multiplexer 13 inputs the detection signals Q1 to Q4 and the detection signals Y1 to Y4 and outputs corresponding control signals Z1 to Z4. Specifically, as the power supply voltage V.sub.CC decreases and/or time passes, the multiplexer 13 sequentially outputs the signal Z1, the signals Z1 and Z2, the signals Z1, Z2, and Z3, and the signals Z1, Z2, Z3, and Z4. The first amplifying circuit is enabled by the control signal Z1, the second amplifying circuit is enabled by the control signal Z2, the third amplifying circuit is enabled by the control signal Z3, and the fourth amplifying circuit is enabled by the control signal Z4.
When the first amplifying circuit is enabled, the gain of the circuit can be represented by the sum of the gain of the P-type transistors 8a and 9a (i.e. .beta.p1) and the sum of the gain of the N-type transistors 10a and 11a (i.e. .beta.n1). When the second amplifying circuit is enabled, the gain of the circuit can be represented by the sum of the gain of the P-type transistors 8b and 9b (i.e. .beta.p2) and the sum of the gain of the N-type transistors 10b and 11b (i.e. .beta.n2). When the third amplifying circuit is enabled, the gain of the circuit can be represented by the sum of the gain of the P-type transistors 8c and 9c (i.e. .beta.p3) and the sum of the gain of the N-type transistors 10c and 11c (i.e. .beta.n3). Finally, when the fourth amplifying circuit is enabled, the gain of the circuit can be represented by the sum of the gain of the P-type transistors 8d and 9d (i.e. .beta.p4) and the sum of the gain of the N-type transistors 10d and 11d (i.e. .beta.n4).
Therefore, when power is initially supplied to the oscillation circuit and causes it to begin oscillating, the multiplexer 13 outputs only the signal Z1. Accordingly, only the first amplifying circuit is enabled, and thus, the gain of the entire amplifying unit 15 equals .beta.p1 on the P-channel side and .beta.n1 on the N-channel side. Then, the multiplexer 13 outputs only the signals Z1 and Z2, and the first and second amplifying circuits are enabled. As a result, the gain of the entire amplifying unit 15 is increased to .beta.p1+.beta.p2 on the P-channel side and .beta.n1+.beta.n2 oil the N-channel side. Afterwards, the multiplexer 13 outputs the signals Z1, Z2, and Z3, and the first, second, and third amplifying circuits are enabled. Therefore, the gain of the entire amplifying unit 15 is further increased to .beta.p1+.beta.p2+.beta.p3 on the P-channel side and .beta.n1+.beta.n2+.beta.n3 on the N-channel side. Finally, the multiplexer 13 outputs all of the control signals Z1, Z2, Z3, and Z4 and the first, second, third, and fourth amplifying circuits are enabled. Therefore, the gain of the entire amplifying unit 15 is maximized and equals .beta.p1+.beta.p2+.beta.p3+.beta.p4 on the P-channel side and .beta.n1+.beta.n2+.beta.n3+.beta.n4 on the N-channel side.
Based on the operation above, the oscillation signal X1 is input to the amplifying unit 15 and amplified in accordance with the control signals Z1 to Z4 to produce the output signal X2. Then, the waveform of the output signal X2 is shaped by a Schmitt trigger circuit (not shown) to produce a clock signal which is used to synchronize the operations of a digital device (e.g. a microcomputer).
As shown above, the gains of the amplifying units of the conventional oscillator circuits can be selectively switched in accordance with one or more control signals. However, when the conventional oscillator circuits are employed in a semiconductor device (e.g. a microcomputer), various problems arise.
For example, when the gain of the amplifying unit is excessively high, a excessive amount of current is consumed. For example, in the amplifying circuits 21 and 22 shown in FIG. 12, a portion of the current which is supplied from the power supply (i.e. I.sub.VDD) is output from the circuits 21 and 22 as the current (i.e. I.sub.X2) of the output signal X2, and a portion of the current I.sub.VDD passes through the amplifying circuits to ground as a ground current (i.e. I.sub.GND). In other words, I.sub.VDD =I.sub.X2 +I.sub.GND. When the gain increases, a greater amount of current I.sub.X2 is output from the amplifying circuits 21 and 22, and thus, the greater amount of current I.sub.VDD is drawn from the power supply. As a result, a greater amount of current I.sub.GND is supplied to ground, and the amount of power consumed by the circuits 21 and 22 is unnecessarily high.
Also, when the gain of the amplifying circuits 21 and 22 is improperly shifted to another gain (e.g. when the voltage of the power supply increases), the oscillator circuit may oscillate at other frequencies other than its preselected oscillation frequency f. For example, the oscillator circuit may be designed to oscillate at a resonant frequency f but may also oscillate at higher level harmonics (e.g. 3 f and 5 f) depending on the gain of the amplifying circuits. Thus, if the gain of the amplifying circuits is excessively high, for example, the oscillator may oscillate at an incorrect frequency 3 f or 5 f.
Also, when the gain is high, an output signal having a frequency f is clamped by the transistors within the amplifying circuits to V.sub.DD, and thus, the output of the amplifying circuits resembles a pulse signal. Also, the pulse signal generates higher level harmonic signals which resonate at 3 f and 5 f. Thus, if the oscillator circuit is designed to resonate at 16 MHz (i.e. f), a noise which has a frequency of 80 MHz (i.e. 5 f) may be generated, and such noise has a frequency which interferes with radio receivers.
On the other hand, when the gain of the amplifying unit becomes excessively low, the oscillating operation of the circuit is frequently interrupted, and thus, the circuit outputs an erroneous clock signal.
Also, in a general-purpose semiconductor device such as a microcomputer, an oscillator circuit is typically used with a wide range of power supply voltages and over a wide range of oscillation frequencies. Thus, the circuit may be required to periodically switch among the different gains of the amplifying unit in response to the varying supply voltages and frequencies.
However, when the gains of the amplifying unit are switched, noise is produced in the oscillator circuit. Thus, if the gains are switched during the operation of the microcomputer, an erroneous clock signal is output, and the microcomputer or the devices controlled by the microcomputer malfunction. As a result, when the gains are switched in a conventional oscillation circuit, they must be switched when the operation of the microcomputer is paused.
An example of how an erroneous clock signal is generated by the conventional circuit shown in FIG. 12 will be described below in conjunction with FIG. 14. The figure illustrates the waveforms of the output signal X2 (FIG. 14(a)) output from the amplifying unit, the ideal gain control signal GAIN1 (FIG. 14(b)), the ideal inverted gain control signal GAIN1* (FIG. 14(c)), the clock signal X0 (FIG. 14(d)) output from the Schmitt trigger circuit 23, the actual gain control signal GAIN1 (FIG. 14(e)), and the actual inverted gain control signal GAIN1* (FIG. 14(f)). (Please note that the change in amplitude of the signal X2 die to the change in the gain is not shown in FIG. 14(a) for the sake of clarity). As shown in the figure, whenever the voltage of the output signal X2 rises above an upper threshold voltage S1 of the Schmitt trigger circuit 23, the circuit outputs an "H" as the clock signal X0. On the other hand, whenever the voltage of the signal X2 drops below a lower threshold voltage S2 of the circuit 23, an "L" is output as the clock signal X0. Therefore, since the output signal X2 is sinusoidal, the circuit 23 outputs a square wave clock signal X0.
As shown in the figure, the gain of the amplifier unit is switched at the time (1) when the value of the gain control signal GAIN1 changes from "L" to "H". When the gain is switched, a noise "a" is generated in the output signal X2, and thus, the voltage of the signal X2 erroneously rises above the upper threshold S1 of the circuit 23. As a result, the noise "a" is output by the Schmitt trigger circuit 23 as a noise "b" in the clock signal X0, and a microcomputer synchronized by the clock signal X0 may malfunction. Also, as shown in FIG. 14(e), the actual gain control signal GAIN1 does not immediately switch from "L" to "H", but changes from "L" to "H" over some time period. Also, as shown in FIG. 14(f), the actual inverted gain control signal GAIN1* switches from "H" to "L" a short time t.sub.D after the actual signal GAIN1 changes due to the delay of the inverter 24. Therefore, the P-type transistor P1 turns OFF slightly before the N-type transistor N2 turns OFF. Thus, during the period t.sub.D when the N-type transistor N2 is ON and the P-type transistor P1 is OFF, the transistor N2 substantially pulls the voltage of the signal X2 down below the threshold S2. Thus, an additional and erroneous pulse in the clock signal X0 output from the Schmitt trigger 23 is generated.